As a serial communication interface through which information is transmitted and received using a clock line and a data line between a plurality of apparatuses, for example, an Inter-Integrated Circuit (I2C®) bus is known. With this type of serial communication interface, a slave that has detected an error of a command transmitted by a master notifies the master of the error by immediately outputting a not acknowledge, without transmitting data for notifying the master of the error (for example, see Japanese Laid-open Patent Publication No. 2014-216738). In addition, a slave receives data in synchronization with a rising edge of a clock and receives a chip enable signal or an identification flag for identifying the type of data in synchronization with a trailing edge of the clock, and as a result the number of clocks for transfer of the data is reduced (for example, see Japanese Laid-open Patent Publication No. 2001-127827).
In contrast, a serial communication interface is known that transmits, from a master to a slave, data on which a clock is superimposed. With this type of serial communication interface, interactive communication is realized by transmitting data from the slave to the master in a period that is included in a period in which data is transmitted from the master to the slave but that is neither a clock extraction period nor a received-data determination period (for example, see Japanese Laid-open Patent Publication No. 2015-5962).